View APU0065_1176707.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

APU0065
PRELIMINARY
40 CH Driver for Dot Matrix LCD
FEATURES
* * * * * Display driving bias ; static-1/5 Power supply voltage ; VDD= +5V 10% VDD= +3V 10% Supply voltage range for display : 10V Negative display voltage : 0 VEE VDD - 10V Interface
Driver (cascade connection) Other APU0065 Controller APU0066
APPLICATIONS
* * * * * * Dot matrix LCD driver with 40 channel output. Selectable function to use Common / Segment drivers simultaneously. Input / Output signal Output ; 20 x 2 channel waveform for LCD driving Input ; - Serial display data and control pulse from the controller LSI . Bias voltage (V1 - V6) QFP64 and bare chip available *
GENERAL DESCRIPTION
The APU0065 is a LCD driver LSI that is fabricated by low power CMOS technology. Basically this LSI consists of 20 x 2bit bi-directional shift register, 20 x 2bit data latch and 20 x 2bit driver. This LSI can be CMOS Process used a Common or Segment driver.
ORDERING INFORMATION
APU0065 E
Handling Code Package Type Q : QFP Y : Chip Handling Code TY : Tray Package Type
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 1 www.anpec.com.tw
APU0065
PRELIMINARY
SC1~SC20 V3 V4 V1 V2 V5 V6 SC21~SC40
End Stage Output Voltage Multiplexor Part1
V 1S V 2S
Pre-Stage Output Voltage Multiplexor Part1 M_1_20
Pre-Stage Output Voltage Multiplexor Part2 M_21_40
V 3S V 4S
End Stage Output Voltage Multiplexor Part2
PART 1
PART 2
latch clock_1_20
LATCH Part1
latch clock_21_40
LATCH Part 2
register clock_1_20 DL1 SHIFT Part 1
Common/Segment Mode Control Signal Convert Part
register clock_21_40 SHIFT Part 2 DR2
SHL1
DR1
CL1
CL2
M
FCS
DL2
SHL2
Figure 1. Block diagram of APU0065
V6
V5
V4
V3
V2
V1
FCS
SHL2 SHL1
M
DR2
DL2
DR1
DL1
V SS
CL2
CL1
VEE
51
SC40 SC39 SC38 SC37 SC36 SC35
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
52 32 53 31 54 30 55 29 56 28 57 27 58
SC6 SC5 SC4 SC3 SC2 SC1
APU0065
26 25
V DD SC7 SC8 SC11 SC10 SC9
SC30 SC31 SC32
59 60 24 61 23 62 22 63 21 64 20 1 2
SC29
SC33 SC34
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SC28 SC27 SC26 SC25 SC24 SC23 SC22 SC21
SC20 SC19 SC18 SC17 SC16 SC15 SC14 SC13 SC12
Figure 2. QFP 64 Top View
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002 2 www.anpec.com.tw
APU0065
PRELIMINARY
PIN DESCRIPTION-QFP100
PAD (NO.)
V EE (33) V D D (25) V SS (36) V 1 ~ V6 (46 ~ 51) M (42) CL1, CL2 (34, 35)
INPUT/ OUTPUT
Power Power Power Input Input Input
NAME
Negative Supply Voltage Operating Voltage Operating Voltage Bias Voltage Altemated signal for LCD driver output Data shift / latch clock
DESCRIPTION
INTERFACE
Power Supply Power Supply Power Supply Power Supply Controller Controller
V DD - 1 0 V) For logical circuit (+5V 10%, +3V 10%)
0V (GND) Bias Voltage level for LCD drive This is the signal for LCD twisting These signal control the shift and latch of driver. More detail scription in next lineF C S. If FCS equals to VSS , Part1 and Part2 both are segment mode. If FCS equals to VDD , Part1 is segment mode but Part2 is common mode .
For LCD driver circuit(0 VEE
FCS (45)
Input
Mode selection
Mode Segment Common
CL1 latch shift shift
CL2
M M M
Controller
latch
Selection of the shift directon of Part 1 shift register SHL1 SHL1 (43) Input Shifting direction control signal of Part1 VDD V SS DL1, DR1 (37, 38) SC1 ~ SC20 Input Output Output DL1 output input DR1 input output Controller or APU0063 LCD Controller
Data interface LCD driver
Data input / output of Part1 shift register LCD driver output of Part1 Selection of the shift directon of Part 2 shift register SHL2 VDD V SS DL2 output Input DR2 Input output
SHL2 (44)
Input
Shifting direction control signal of Part2
Controller
DL2, DR2 (39, 40) SC21 ~ SC40
Input Output Output
Data interface
Data input / output of Part 2 shift register
Controller or APU0063 LCD
LCD driver
LCD driver output of Part2
Note : Input pin can not be floated, or it will cause large leakage current.
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
3
www.anpec.com.tw
APU0065
PRELIMINARY
COMMON MODE
Only Part2 can be selected to work in common mode (FCS pin = VDD). These are the liquid crystal common drive outputs signal of driving pin in segment mode is the one of V1, V2,, V5 or V6. These selecting are following.
SEGMENT MODE
When Part1 or Part2 be selected to work in segment mode (FCS pin = VSS), these are the liquid crystal segment drive outputs. A signal of driving pin in segment mode is the one of V1, V2, V3 or V4. These selecting are following.
Data of latch High High Low Low
M High Low High Low
Output voltage V1 V2 V3 V4
Data of latch High High Low Low
M High Low High Low
Output voltage V2 V1 V6 V5
SHIFT DIRECTION SPECIFICATION
Part1 Part2
When Part2 shift direction control signal, SHL2, is set to VSS. Now the Part1 register shift direction is DL2 SC21 SC22 . . . SC39 SC40 DR2 Otherwise,when SHL2 is set to VDD.Its direction is DL2 SC21 SC22 . . . SC39 SC40 DR2 When Part1 shift direction control signal, SHL1, is set to VSS. Now the Part1 register shift direction is DL1 SC1 SC2 . . . SC19 SC20 DR1 Otherwise,when SHL1 is set to VDD.Its direction is DL1 SC1 SC2 . . . SC19 SC20 DR1
MAXIMUM ABSOLUTE LIMIT (Ta = 25 C)
Characteristic
Operating Voltage Driver Supply Voltage Input Voltage 1 Input Voltage 2 (V1 ~ V 6 ) Operating Temperature Storage Temperature
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
Symbol
VDD V LCD V IN1 V IN2 T OPR T STG
4
Value
-0.3 ~ +7.0 V D D -13.5 ~ VD D +0.3 -0.3 ~ VD D +0.3 V D D +0.3 ~ VE E -0.3 -30 ~ +85 -55 ~ +125
Unit
V V V V
o o
C C
www.anpec.com.tw
APU0065
PRELIMINARY
ELECTRICAL CHARACTERISTICS
DC characteristics (VDD = 2.7 ~ 5.5V, 0 VEE VDD - 10V, VSS = 0V, Ta = -30 ~ +85 C)
Characteristic
Operating Current* Supply Current* Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Voltage Descending
Symbol
IDD I EE V IH V IL I LKC V OH V OL V D1 V D2
Test condition
f CL2 = 4 0 0 K H z f CL1 = 1KHz _ V IN = 0 - V D D I OH = -0.4mA I OL = +0.4mA
I O N = 0.1mA for one of SC1 ~ SC40 IO N = 0.05mA for each SC1 ~ SC40
Min
_ _ 0.7 V D D 0 -5 V DD - 0.4 _ _ _
Max
1 10 V DD 0.2 V D D 5 _
Unit
mA A V A
Applicable pin
_
CL1, CL2, DR1, DR2, DR1, DR2, SHL1, SHL2, M, FCS
DL1, DL2, DR1, DR2 0.4 V 1.1 1.5 10 A V ( V1 ~ V6 ) SC ( SC1 ~ SC40 )
Leakage Current
IV
V IN = V DD ~ V EE (Output SC1 ~ SC40 : floating)
-10
V 1 ~ V6
AC characteristics (VDD = 2.7 ~ 5.5V, 0 VEE VDD - 10V, VSS = 0V, Ta = -30 ~ +85 C)
Characteristic
Data shift Frequency Clock High Level Width Clock Low Level Width Clock Set-up Time Clock Rise / Fall Time Data Set-up Time Data Hold Time Data Delay Time
Symbol
f CL tW C K H tWCKL t SL t LS tR / tF t SU tDH tD
Test condition
_ _ _ from CL2 to CL1 from CL1 to CL2 _ _ _
Min
_ 800 800 500 500 _ 300 300 _
Max
400 _ _ _ _
Unit
KHz
Applicable pin
CL2 CL1,CL2 CL2
CL1,CL2 ns
200 _ _ 600 DL1,DL2,DR1,DR2,FLM
DL1,DL2,DR1,DR2
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
5
www.anpec.com.tw
APU0065
PRELIMINARY
TIMING CHARACTERISTICS
V IH tWCKL V IL tR tW C K H tF tD H tS U V IL V IH
CL2
Data in (DL1,DL2) (DR1,DR2)
V IH V IL
tD
tSL
Data out (DR1,DR2) (DL1,DL2)
V OH V OL V IH V IL tR V IH V IL
tLS
tLS
CL1
tW C K H tSU tF
FLM
Figure 3. Timing diagram of signals
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
6
www.anpec.com.tw
APU0065
PRELIMINARY
FUNCTIONAL DESCRIPTION
1) Segent mode
M
Latch
CL1
Shift
CL2 DL1 / DR1 DL2 / DR2 OUTPUT OF LATCH (SC)
SC1 SC2 SC39 SC40
SC1~SC40
When the FCS is connected to VSS, APU0065 (SC1 ~ SC40) is operated as segment driver. (refer to figure 5) Figure 4. timing diagram of Segment mode 2) Common mode
DL2 / DR2
M
Shift
CL1
Latch
CL2 OUTPUT OF LATCH (SC)
SC21~SC40
When the FCS is connected to VDD, only part2 (SC21 ~ SC40) of APU0065is operated as common driver. (refer to figure 6.) Figure 5. timing diagram of Common mode
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
7
www.anpec.com.tw
APU0065
FCS OUTPUT OF LATCH (DATA)
PRELIMINARY
M
V2 V4 V3 V3 V2 V4
PART 1 (SC1 ~ SC20)
V1 V2 V5
V1 V2 V5
PART 2 (SC21 ~ SC40)
V6 V1 V1 V6
Note : When fcs equals to high voltage, PART 2 (SC21 ~ SC40) is operated as LCD Common driver. PART 1 (SC1 ~ SC20) always be operated as LCD segment driver, no matter fcs equals to high or low Figure 6. SC1 ~ SC40 output waveform
Customer Service
Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
8
www.anpec.com.tw
APU0065
PRELIMINARY
APPLICATION CIRCUIT
1. Segment driver
APU0066 (controller)
COM1 ~ COM16 common signal SC1~SC40
LCD
M
CLK2
CLK1
D
SHL1 SHL2 FCS DL1 DR1 DL2
SHL1 SHL2 FCS DR2 DL1 DR1 DL2
SC1~SC40
APU0065 (Seg driver)
APU0065 (Seg driver)
DR2 M OPEN
CL1
CL2
M
CL1
CL2
2. Segment / Common driver
Common signal LCD Segment signal Controller D FLM M CL1 CL2 V DD FCS SHL1 SHL2 CL2 CL1 SC21~SC40 DL1 DL2 SC1~SC20 FCS SHL1 SHL2 DL1 DR1 DL2 SC1~SC40 DR2 APU0065 (Seg driver) OPEN
APU0065 (Seg / Com driver) DR1 M
CL2
CL1
M
Figure 7. Connection between APU0065 and Controller
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
9
www.anpec.com.tw
SC12 18 17 16 15 14 13 12 11 10 9 8 7 6 5
SC13 SC14 SC15 SC16 SC17 SC18 SC19 SC20 SC21 SC22 SC23 SC24 SC25 SC26 4
SC27 3
SC28 2
SC9 19 S C 1 0 20 S C 1 1 21 SC8 22 23 24 25 26 27 28 29 30 31 32 CL1 33 CL2 34 VSS 35 DL1 36 DR1 37 DL2 38 DR2 40 M 41 42 SHL1 SHL2 43 FCS 44 V1 SC7 V DD SC6 SC5 SC4 SC3 SC2 SC1
1
SC29
60
SC34
new pad coordinate of
59
SC33
APU0065
58
SC32
57
SC31
56
SC30
55
SC35
PRELIMINARY
54
SC36
52
SC38
(0.0) is the center of the chip
51
SC39
50
SC40
V EE
V6 45 V2 46 V3 47 V4 48 V5
49
V6
Figure 8. Chip pad arrangement
APU0065
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
Chip size : Pad size : Pitch length Unit :
2010 x 1670 80 x 80 : 100 m
53
SC37
10
(0.0)
www.anpec.com.tw
APU0065
PRELIMINARY
PAD LOCATION
PAD NUMBER PAD NAME
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SC29 SC28 SC27 SC26 SC25 SC24 SC23 SC22 SC21 SC20 SC19 SC18 SC17 SC16 SC15 SC14 SC13 SC12 SC9 SC10 SC11 SC8 SC7 VDD SC6 SC5 SC4 SC3 SC2 SC1
COORDINATE X Y
902.5 850.0 725.0 600.0 500.0 400.0 300.0 200.0 100.0 0.0 -100.0 -200.0 -300.0 -400.0 -500.0 -600.0 -725.0 -850.0 -902.5 -902.5 -902.5 -902.5 -902.5 -902.5 -902.5 -902.5 -902.5 -902.5 -902.5 -902.5 630.0 732.5 732.5 732.5 732.5 732.5 732.5 732.5 732.5 732.5 732.5 732.5 732.5 732.5 732.5 732.5 732.5 732.5 630.0 525.0 420.0 315.0 210.0. 105.0 0.0 -105.0 -210.0 -315.0 -420.0 -525.0
PAD NUMBER
31 32 33 34 35 36 37 38 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
PAD NAME
VEE CL1 CL2 VSS DL1 DR1 DL2 DR2 M SHL1 SHL2 FCS V1 V2 V3 V4 V5 V6 SC40 SC39 SC38 SC37 SC36 SC35 SC30 SC31 SC32 SC33 SC34
COORDINATE X Y
-902.5 -800.0 -700.0 -600.0 -500.0 -400.0 -300.0 -200.0 -100.0 0.0 100.0 200.0 315.0 430.0 545.0 660.0 775.0 905.0 902.5 902.5 902.5 902.5 902.5 902.5 902.5 902.5 902.5 902.5 902.5 -630.0 -722.5 -732.5 -732.5 -732.5 -732.5 -732.5 -732.5 -732.5 -732.5 -732.5 -732.5 -732.5 -732.5 -732.5 -732.5 -732.5 -632.5 -525.0 -420.0 -315.0 -210.0 -105.0 0.0 105.0 210.0 315.0 420.0 525.0
Copyright ANPEC Electronics Corp. Rev. A.07 - FEB., 2002
11
www.anpec.com.tw

▲Up To Search▲

Price & Availability of APU0065

	To Download APU0065 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .